First, the method of setting the optimum threshold level for a comparator that compares an unknown voltage input in an error detector to an optimum value will be described.
As shown in FIG. 6 (b), the DUT receives the test pattern or PRBS data pattern from a pattern generator. The error detector then measures the error rate in the output pattern from the DUT.
FIG. 6 (b) also shows an example of the circuit configuration. The pattern generator is connected to the DUT and the DUT is connected to the error detector. In this configuration, the pattern generator provides a test pattern and a clock output to the DUT. Subsequently, the output from the DUT, which includes an input pattern 111 and a clock input 110, is sent to the error detector.
Conventionally, the threshold voltage of the error detector is suitably adjusted to correspond to the input voltage. This adjustment is made prior to the measurement of the input voltage by the error detector.
FIG. 6 (a) shows a configuration of a conventional error detector.
For accurate measurements, it is necessary to set a voltage Vt and a clock delay time to an optimum operating point 142, as shown in FIG. 6 (c).
There are two methods for adjusting the threshold voltage to correspond to the input pattern voltage that the DUT outputs.
One method of adjusting the threshold voltage comprises the following steps. First, pre-measurements of the high and low levels of the input pattern 111 are made utilizing a sampling oscilloscope. Next, the mesial value between the high and low levels is calculated. Finally, a variable resistor 113 is adjusted so that the threshold voltage Vt is at the calculated mesial value.
Another method of adjusting the threshold voltage, which is the preferred method, comprises the following steps. First, a pattern similar to the reference pattern 119 is supplied to the error detector instead of the input pattern 111. Next, both the variable resistor 113 and the variable delay part 114 are manually adjusted so that the error-counter 118 does not count errors. Finally, there is a search for an optimum operating point 142.
The method of searching for an optimum point will now be described. However, it should be noted that there exists an error free state, hereinafter referred to as the error free state, in which no errors are detected. The error free state corresponds to the operating area 141, shown in FIG. 6 (c). The search is conducted in the operating area and, subsequently, the optimum operating point 142 is located within the operating area.
The method of searching for the optimum point comprises the following steps. First, the variable resistor 113 and the variable delay part 114 are properly adjusted so that the voltage Vt and the clock delay time are located within the operating area 141, which is the error free state. Next, the voltage Vt is adjusted to obtain an upper limit voltage and a lower limit voltage. The upper limit and lower limit voltages define the voltage Vt range in the error free state. Finally, a mesial value between the upper limit voltage and the lower limit voltage is set as the optimum operating point 142 of Vt.
It should be noted that the Vt range also depends upon the clock delay time. However, since the Vt is set as the mesial value, the clock delay time hardly influences the Vt value.
The method of adjusting the threshold voltage requires a great amount of time, due to numerous repetitions of the above described procedure to locate the optimum operating point 142.
Referring to FIG. 6 (a), an input pattern 111 is compared to a set threshold voltage Vt by a comparator 112. The comparator 112 outputs a shaped signal 132 with definite high and low levels. Next, the shaped signal 132 is changed by the clock input 133 at the flip-flop 115, which results in restored output data 134. Further, an error comparing part 117 compares the restored data 134 to the output pattern of a reference-pattern-generating part 119. If differences between the data and output pattern are found, the clock 133 changes the error comparing part 117 to output a counting pulse 135. Finally, the output pulse 135 is counted by the error counter 118.
For this case, the reference-pattern-generating part 119 is a pattern generator used for referencing the input pattern 111 and, subsequently, generating the same pattern as the input pattern.
The phase adjustment of a pattern-synchronizing circuit used for an error-detecting apparatus will be described below. FIG. 7 shows an example of a conventional pattern-synchronizing circuit and FIG. 8 shows an example of a test configuration for a DUT 51. Referring to FIGS. 7 and 8, the conventional technology will now be described.
Referring to FIG. 8, a pattern generator 50, which is connected to a DUT 51, outputs a testing input pattern signal 53, that is already-known data, PRBS data or the like, and an input clock signal 54. The DUT, which is connected to an error-detecting apparatus 52, outputs an output pattern signal 55 and a clock signal 56 to a pattern-synchronizing circuit 10 of the error-detecting apparatus 52.
For this example, the DUT and connecting cables create a propagation delay in the output signals. This typically occurs at high frequencies (i.e. up to 10 GHz). As a result, there is a phase difference between the two types of input signals received by the pattern synchronizing circuit 10. Accordingly, signal synchronization in the circuit is not realized.
For this reason, an operator must wait until synchronization is established. Synchronization is established by manually adjusting a variable delay element 14. An example of an available variable delay element is a delay line with a resolution of 10 PS, controlled by a motor drive controller.
FIG. 7 shows an example of a conventional pattern synchronizing circuit. A pattern data 30 is input to a port of a comparator 11. Next, a voltage from a reference voltage generator 12 is input to the other port of the comparator 11 as a threshold voltage. The comparator 30 then converts the pattern 30 into a digital signal which is input to a re-timing circuit 13.
A clock 31 is applied to the re-timing circuit 13 as clock input 32 via the manual variable delay element 14. Thus, the digital signal is synchronized by the clock 32 in the re-timing circuit 13. Subsequently, the re-timing circuit 13 outputs a demodulated signal 33. At this time, however, since the output data 33 is not necessarily synchronized with a correct phase, the output data 33 is temporarily stored.
Next, the output data 33 is applied to a port of a code-error detecting circuit 16. The reference pattern data 34 originating from a reference pattern generating circuit 15 is applied to the other port of the circuit 16. Then, the circuit 16 compares the two data according to the input clock 32. If the two data are not coincident with each other, the circuit 16 outputs an error pulse 35.
Next, an error rate detecting divider 17, which is used for synchronous detection, counts the error pulses. In contrast, an error counter 18 is a real error rate measuring circuit and is not used for synchronous detection.
For this example, the error rate detecting divider 17 is also a simple error rate measuring unit. In other words, whenever more than 10 raised to the power of -3 errors are detected, an error pulse signal 36 is output by the divider 17.
The output data 34 from the reference pattern generating circuit 15 is delayed by only one bit from this error pulse signal 36. In other words, receipt of an error pulse 36 by control circuit 21 generates an output inhibiting pulse 37 of one clock time, which subsequently inhibits one clock pulse at a gate 22. Thus, one pulse of a clock source 38 for the reference pattern generating circuit 15 is deleted.
As a result, the reference-pattern-generating circuit 15 generates a reference pattern output which is delayed by one bit. Furthermore, this reference pattern which is delayed by one bit comprises a new data pattern which is applied to the port in the circuit 16. Once again, a data pattern comparison is made by circuit 16.
This series of operations is repeated until the synchronization of the input pattern 30 and the reference pattern delayed by one bit is completed. Thus, when an error pulse 36 does not occur in the designated set amount of time, the inhibiting control circuit 21 outputs a signal 39 that indicates that the synchronization is complete.
It should be noted that even if the clock 32 is synchronized with the output of the comparator 11, but the output 33 of the re-timing circuit 13 does not correspond to the reference pattern 34 in its bit string, then pattern synchronization is not established. Therefore, as mentioned above, the bit string is sequentially shifted by one bit until the pattern strings correspond.
Thus, pattern synchronization requires both synchronization of the clock to the output of the comparator 11 and correspondence of the bit sting of the reference pattern to the bit string of the input pattern.
For this reason, it takes a great amount of time to detect pattern synchronization. In some cases, it may be necessary to generate an inhibiting pulse for a complete cycle of the pattern length until their pattern strings correspond. For example, a bit string length of 1 Kbits requires an output of one thousand inhibiting pulses.
Hereinafter, the repetitive operation performed to detect pattern synchronization will be referred to as a pattern search operation.
FIG. 9 shows the relationship between input data 60 and input clocks 63, 64, and 65. The conventional pattern synchronization procedure will now be described.
Referring to FIG. 9, the input data 60 has a dead zone 61 that is not defined under re-timing. This zone represents a phase area wherein the influence of, for example, a transition time affecting the amplitude of the input data, a jitter in the input data, a set-up-hold time affecting the re-timing flip-flop, or a jitter in the re-timing clock itself, causes the re-timing output data to be undefined.
Hereinafter, this undefined area will be referred to as the dead zone. It should be noted that as the clock rate increases up to 10 GHz, this dead zone also expands. As a result, the acceptable range 62 contracts.
The conventional pattern synchronization procedure includes the following steps. First, the phase of the input data and the clock are adjusted, as shown by clock input 63. However, since the leading edge of the input clock 63 is positioned in the dead zone 61, the input data and the input clock 63 will not become synchronized. Even if a time period greater than a complete cycle of the input pattern passes, pattern synchronization will not occur.
Next, a variable delay element 14 is adjusted, as shown by input clock 64. Likewise, since the leading edge of the input clock 64 is also positioned in the dead zone 61, the input data and the input clock 64 will not become synchronized. Once again, even if a time period greater than a complete cycle of the input pattern passes, pattern synchronization will not occur.
However, when the leading edge of the input clock, as shown by input clock 65, is positioned in the effective permissible range 62, pattern synchronization occurs.
Since the above operation is continuously repeated until pattern synchronization is detected, a great amount of time is wasted.
Variations in ambient temperature and jitter may cause the data measured by the error test to shift to an unstable point. Thus, if the error test (used for synchronous detection) is performed in this type of setting, the timing shown by clock 65 does not necessarily provide a stable measurement.
Therefore, it is apparent that it is necessary to obtain a range of time which provides a stable operation.
The method of obtaining a range of time comprises the following steps. First, the variable delay element 14 is adjusted so as to obtain two clock delay times wherein pattern synchronization is realized. Next, the delay time of the variable delay element 14 is set at a point located in the middle between the two delay times. This point is known as the optimum operating point. Once this is accomplished, as actual stable error test can be performed.
The round time of the input pattern is defined as the pattern length that an operator sets in the pattern generator 50, shown in FIG. 8. For example, a PRBS pattern of 23 bits has a pattern length of 2 to the 23rd power. The minimum time required to perform a pattern-searching operation one time for a pattern rate of 10 GHz, is about 10 seconds [which is 2 to the 23rd power .times. 10 to the third power .times. clock time (i.e. 10 to the ninth power)]. Thus, conventional pattern synchronization procedures involving multiple adjustments of the variable delay element require a greater amount of time than the round time.
Further, conventional pattern-synchronizing operations should be performed whenever the conditions of either a clock or a pattern data for an actual error test is changed. Whenever an operator changes an output condition of a pattern generator, the above mentioned procedure must be performed. In addition, a search for the optimum operating point must also be performed, thereby making the above described procedures undesirable.